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3 ghz hdmi 5: 1 transceiver with on - scr een display data sheet adv7627 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third partie s that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respectiv e owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 5 - input, 1 - output hdmi transceiver hdmi support 3 ghz video support ( up to 4k 2k) audio return channel (arc) 3d tv support content type bits cec 1.4 - compatible extended colorimetry character - and icon - based on - screen display (osd) 3d osd overlay on all mandatory 3d formats support for osd overlay on 3 ghz video formats high - b andwidth digital content protection (hdcp 1.4) hdcp repeater support : u p to 127 ksvs supported 300 mhz maximum tmds clock frequency (up to 4k 2k) 48- / 36 - / 30- bit d eep c olor input modes supported ultralow jitter digital pll (100% deskew) ttl pixel port input a llows digital video input to facilitate analog video support inter laced - to - progressive converter hdmi receiver for 5 input ports 3 ghz support on all inputs adaptive equa lizer for cable lengths up to 30 meters flexible internal edid ram supports dual edids replication of either dual edid on any input port 5 v detect inputs hot p lug assert control outputs hdmi transmitter 3 ghz support on transmitter outputs edid data extra ction hot p lug detect (hpd) input s audio return channel (arc) receiver 3 ghz c olor space converter (csc) audio hdmi - compatible audio interface 8 - channel audio extraction port 8 - channel audio insertion port s/pdif (iec 60958 - compatible) digital audio input/ output super a udio cd ? (sacd) with dsd input/output interface high bit rate (hbr) audio dolby? truehd dts - hd master audio? full audio input and output support general interrupt controller s tandard identification (stdi) circuit software libraries, driver , a nd application available applications avr htib sound bar with hdmi repeater support other repeater applications functional block dia gram hdmi_rx_ a tmds hdmi tx cp-lite osd rx edid with replic a t or tx edid/hdc p controller interrupts spi i 2 c pixe l port input 5:1 mux digi t a l audio input port digi t a l audio output port hdmi_tx cec hdmi_rx_b hdmi_rx_c hdmi_rx_d hdmi_rx_e ddc tmds hdc p arc ddc tmds ddc tmds ddc tmds ddc tmds ddc adv7627 hd m i r x hdc p 1 1833-001 figure 1.
adv7627 data sheet rev. 0 | page 2 of 24 table of contents fe atures .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision hist ory ............................................................................... 2 general description ......................................................................... 3 detailed functional block diagram .............................................. 4 specifications ..................................................................................... 5 digital, hdmi, and ac specifications ...................................... 5 data and i 2 c timing characteristics ......................................... 6 power specifications .................................................................. 12 absolute maximum ratings .......................................................... 14 package thermal performance ................................................. 14 esd caution ................................................................................ 14 pin configuration and function descriptions ........................... 15 power supply rec ommendations ................................................. 21 power - up sequence ................................................................... 21 power - down sequence .............................................................. 21 theo ry of operation ...................................................................... 22 hdmi receiver ........................................................................... 22 hdcp repeater functionality ................................................. 22 digital audio ports .................................................................... 22 on - screen display ..................................................................... 22 pixel port input ........................................................................... 22 hdmi transmitter ..................................................................... 22 i 2 c interface ................................................................................ 22 other features ............................................................................ 22 outlin e dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 1 2 /13 rev ision 0: initial version
data sheet adv7627 rev. 0 | page 3 of 24 general description the adv7627 is a high performance, five - input, one - output, high - definition multimedia interface (hdmi ? ) transceiver . t he adv7627 supports 3 ghz video and features one hdmi receiver , one hdmi transmitter, an audio output port, an audio input port , and a pixel port input. the adv7627 supports all hdcp repeater functions through fully tested analog devices, inc., repeater sof tware libraries and drivers. the hdmi receiver and transmitter in the adv7627 support the reception and transmission of 3 ghz video formats up to 4k 2k at 24 hz/25 hz/30 hz, in addition to all mandatory hdmi 3d tv formats. the receiver and transmitter also provide support for thx? media director?. the hdmi receiver features an integrated equalizer that ensures robust operation of the interface with cable lengths up to 30 meters. the hdmi receive r has a 768 - byte volatile extended display identification data ( edid ) memory , which can facilitate one or two edids . each hdmi port features dedicated 5 v d etect and h ot p lug ? assert pins. the hdmi transmitter supports audio return channel (arc) and featur es an integrated hdmi cec controller that supports capability discovery and control (cdc). the adv7627 offers an audio output port and an audio input port. each audio port supports the extraction and insertion of up to eight channels of audio data out of or into the hdmi streams. hdmi audio formats, including i 2 s, s/pdif, direct stream digital (dsd) , and high bit rate (hbr) audio are supported. the adv7627 features a ttl pixel port input that facilitates the reception of digital video data from an analog front - end decoder ( for example, the adv7180 , adv7181d , or adv7842 ). the adv7627 has an integrated on - screen display (osd) generator that enable s th e creation and control of high quality character - and icon - based system status and control displays. th e osd can be overlaid on 3 ghz video formats and 3d video. customers who are interested in using osd are provided with blimp, the analog devices osd deve lopment tool. the adv7627 is provided in a space - saving, 260 - ball , 15 mm 15 mm csp_ bga surface - mount, rohs - compliant package and is specified over the 0c to 70c temperature range.
adv7627 data sheet rev. 0 | page 4 of 24 detailed functional block dia gram sampler hdmi rx interrupt controller int1 ep_cs spi hdc p keys memor y tx hpd/arc equalizer plls 5v detect hp a contro l ddc contro l rx audio extraction cec cec master tx edid/hdc p controller tx_hpd_arc? osd blend osd *pins for pixe l port input signals p15 t o p8 are shared with ap_in audio input port pins. hdmi tx pixe l port input p15* p0* tx audio insertion cp-lite 4:2:2 t o 4:4:4 xt al+ i 2 c controller scl clock gener a tion tx pl l digi t al audio output port ap_out0 ap_out5 digi t al audio input port ap_in0*/aud_in ap_in5*/aud_in_lrclk ddc_scl_tx ddc_sda_tx tx_0 tx_1 tx_2 tx_c xt al? rxa_h p a rxb_h p a rxc_h p a rxd_h p a rxe_h p a rxa_5v rxb_5v rxc_5v rxd_5v rxe_5v rxa_0 rxa_1 rxa_2 rxb_0 rxb_1 rxb_2 rxc_0 rxc_1 rxc_2 rxd_0 rxd_1 rxd_2 rxe_0 rxe_1 rxe_2 rxa_c rxb_c rxc_c rxd_c rxe_c ddc_scl_rx a ddc_sda_rx a ddc_scl_rxb ddc_sda_rxb ddc_scl_rxc ddc_sda_rxc ddc_scl_rxd ddc_sda_rxd ddc_scl_rxe ddc_sda_rxe sda alsb cs tx_arc+ ap_in_sclk*/aud_in_sclk ap_in_mclk* arc csc dcm hdc p hdc p sampler equalizer sampler equalizer sampler equalizer sampler equalizer ap_out_sclk ap_out_mclk hs vs de pclk ep_sclk ep_miso ep_mosi int2 1 1833-002 interlaced- t o-progressive (480i/576i on l y) figure 2. detailed functional block diagram
data sheet adv7627 rev. 0 | page 5 of 24 specifications av dd_t x = 1.8 v 5%, cvdd = 1.8 v 5%, dvdd = 1.8 v 5%, dvddio = 3.3 v 5%, pvdd = 1.8 v 5%, pvdd_tx = 1.8 v 5%, tvdd = 3.3 v 5%, t min to t max = 0c to 70c. digital, hdmi, and a c specifications table 1 . parameter test conditions/comments min typ max unit digital inputs input high voltage (v ih ) 2 v input low voltage (v il ) 0.8 v input leakage cur rent (i in ) ? 60 +60 a input capacitance (c in ) 20 pf digital inputs (5 v tolerant) 1 input high voltage (v ih ) 2.85 v input low voltage (v il ) 0.8 v input leakage current (i in ) rxa_5v, rxb_5v, rxc_5v, rxd_5v, rxe_5v ? 450 +450 a all oth er 5 v tolerant digital inputs ? 60 +60 a digital outputs output high voltage (v oh ) 2.4 v output low voltage (v ol ) 0.4 v high impedance leakage current (i leak ) 10 a output capacitance (c out ) 20 pf digital outputs (5 v tolerant) 2 output high voltage (v oh ) 4.85 v output low voltage (v ol ) 0.4 v ac specifications tmds input clock range 25 300 mhz tmds output clock frequency 25 300 mhz 1 the following pins are 5 v tolerant inputs : ddc_scl_rxa , ddc_sda_rxa , ddc_scl_rxb , ddc_sda_rxb , ddc_scl_rxc , ddc_sda_rxc , ddc_scl_rxd , ddc_sda_rxd , ddc_scl_rxe , ddc_sda_rxe , rxa_5v, rxb_5v, rxc_5v, rxd_5v, rxe_5v, cec , ddc_scl_tx , ddc_sda_tx , tx_hpd_arc ?, and tx _arc+ . 2 the following pins are 5 v tolerant outputs : rxa_hpa , rxb_hpa , rxc_hpa , rxd_hpa , and rxe_hpa .
adv7627 data sheet rev. 0 | page 6 of 24 data and i 2 c timing characteris tics table 2 . parameter symbol test conditions/comments min typ max unit video system clock and xtal crystal nominal frequency 27.0 mhz crystal frequency stability 50 ppm external clock source external crystal must operate at 1.8 v inpu t high voltage v ih xtal driven with external clock source 1.2 v input low voltage v il xtal driven with external clock source 0.4 v pixel port input clock frequency range interlaced - to - progressive converter not enabled 13.5 148.5 mhz interlaced - to - progressive converter enabled (480i, 576i) 13.5 mhz serial port ep_sclk frequency 27 mhz audio sclk frequency 49.152 mhz audio mclk frequency 98.304 mhz audio dsd clock frequency 5.6448 mhz reset feature reset pulse width 5 ms i 2 c ports (fast mode) xcl frequency 1 400 khz xcl minimum pulse width high 1 t 1 600 ns xcl minimum pulse width low 1 t 2 1.3 s start condi tion hold time t 3 600 ns start condition setup time t 4 600 ns xda setup time 2 t 5 100 ns xcl and xda rise time 1 , 2 t 6 300 ns xcl and xda fall time 1 , 2 t 7 300 ns setup time (stop condition) t 8 0.6 s serial port , master mode 3 , 4 spi mode 0 ep_ cs falling edge to ep_sclk rising/ falling edge t 9 , t 10 1 ep_sclk periods 1.5 ep_sclk periods ns ep_sclk rising/falling edge to ep_ cs rising edge t 11 , t 12 1 ep_sclk periods 1.5 ep_sclk periods ns ep_ cs pulse width 5 t 13 1000 ns ep_sclk high time t 14 40 60 % duty cycle ep_sclk low time 40 60 % duty cycle ep_mosi start of data invalid to ep_sclk falling edge t 15 0 ns ep_ cs start of data invalid to ep_sclk falling edge t 15 0 ns ep_sclk falling edge to ep_mosi end of data invalid t 16 2.15 ns ep_sclk falling edge to ep_ cs end of data invalid t 16 2.15 ns ep_miso setup time t 17 valid regardless of the ep_sclk active edge used 7.5 ns ep_miso hold time t 18 valid re gardless of the ep_sclk active edge used 0 ns
data sheet adv7627 rev. 0 | page 7 of 24 parameter symbol test conditions/comments min typ max unit serial port, slave mode 3 , 4 spi mode 0 ep_ cs falling edge to ep_sclk rising edge t 20 10 ns final ep_sclk rising edge to ep_ cs rising edge t 22 10 ns ep_ cs pulse width 5 t 23 20 ep_sclk periods ns ep_sclk high time t 24 45 55 % duty cycle ep_sclk low time 45 55 % duty cycle ep_mosi setup time t 25 0.5 ns ep_mosi hold time t 26 1.4 ns ep_sclk falling edge to ep_miso start of data invalid t 27 5.5 ns ep_sclk falling edge to ep_miso end of data invalid t 28 9 ns video data an d control inputs pclk high time 5 t 29 0.45 to 0.55 pclk period % duty cycle pclk low time 5 0.45 to 0.55 pclk period % duty cycle pixel port input , setup time, sdr and ddr modes t 30 data latched on rising edge 1.0 ns pixel port input, hold time, sdr and ddr modes t 31 data latched on rising edge 1.4 ns pixel port input, setup time, ddr mode t 32 data latched on falling edge 1.0 ns pixel po rt input, hold time, ddr mode t 33 data latched on falling edge 1.4 ns audio input port , i 2 s input ap _in_sclk high time t 37 45 55 % duty cycle ap _in_sclk low time 45 55 % duty cycle ap _in data setup time t 38 2.3 ns ap _in data hold time t 39 1.6 ns aud _in_sclk high time t 37 45 55 % duty cycle aud _in_sclk low time 45 55 % duty cycle aud _in data setup time t 38 1.0 ns aud _in data hold time t 39 3.5 ns audio input port, dsd input ap _in_sclk high time t 40 45 55 % dut y cycle ap _in_sclk low time 45 55 % duty cycle ap _in dsd data setup time t 41 2.3 ns ap _in dsd data hold time t 42 1.6 ns audio ou tput port , i 2 s output ap _out_sclk high time t 46 45 55 % duty cycle ap _out_sclk low time 45 55 % duty c ycle ap _out lrclk transition time t 47 start of invalid lrclk to falling ap _out_sclk edge 10 ns ap _out lrclk transition time t 48 falling ap _out_sclk edge to end of invalid lrclk 10 ns
adv7627 data sheet rev. 0 | page 8 of 24 parameter symbol test conditions/comments min typ max unit ap _out data transition time t 49 start of invalid data to falling a p _out_sclk edge 10 ns ap _out data transition time t 50 falling ap _out_sclk edge to end of invalid data 10 ns audio output port , dsd output ap _out_sclk high time t 51 45 55 % duty cycle ap _out_sclk low time 45 55 % duty cycle ap _out dsd da ta transition time t 52 start of invalid data to falling ap _out_sclk edge 10 ns ap _out dsd data transition time t 53 falling ap _out_sclk edge to end of invalid data 10 ns 1 xcl refers to scl, ddc_scl_r x a, ddc_scl_r x b, ddc_scl_r x c, ddc_scl_r x d, and ddc_scl_r x e. 2 xda refers to sda, ddc_sda_r x a, ddc_sda_r x b, ddc_sda _r x c, ddc_sda_r x d, and ddc_sda_r xe. 3 spi mode 0 only. 4 all serial port measurements are for cpha = 0, cpol = 0 (clock is low in idle state ; negative edge of clock is used to transmit data and positive edge is used to sample data). 5 measurements guarante ed by design only. timing diagrams xd a xc l t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 1 1833-003 figure 3. i 2 c timing instruction (0x0b) 24-bit address dumm y byte 7 6 5 4 3 2 1 0 dat a out 2 ep_mosi ep_miso 7 6 5 4 3 2 1 0 dat a out 1 ep_sclk ep_cs t 1 1 t 13 t 12 t 9 t 10 23 22 21 ... 3 2 1 0 7 6 5 4 3 2 1 0 1 1833-004 figure 4 . detailed spi master ti ming diagram (spi mode 0, cpol = cpha = 0) ep_sclk ep_mosi ep_miso ( f alling edge capture) ep_miso (rising edge capture) t 17 t 15 t 16 t 18 t 17 t 18 t 14 ep_cs 1 1833-005 figure 5. spi master mo de timing (spi mode 0)
data sheet adv7627 rev. 0 | page 9 of 24 device address subaddress d at a in 0 d at a in 1 dumm y byte d at a out 0 d at a out 0 d at a out 1 w/r 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 t 23 t 22 ep_mosi del a y mode 1 ep_miso del a y mode 0 ep_miso ep_sclk t 20 ep_cs 1 1833-006 figure 6 . detailed spi slave timing diagram (spi mode 0, cpol = c pha = 0) ep_sclk ep_mosi ep_miso t 24 t 25 t 26 t 27 t 28 1 1833-007 figure 7. spi slave mode timing (spi mode 0) pclk t 29 t 30 t 31 p[15:0] hs vs de 1 1833-008 figure 8. pixel port i nput, n oninterleaved sdr v ideo d ata and c ontrol t iming t 33 t 32 t 31 t 30 t 29 pclk p[15:0] hs vs de 1 1833-009 figure 9. pixel port i nput, n oninterleave d ddr v ideo d ata and c ontrol t iming
adv7627 data sheet rev. 0 | page 10 of 24 t 39 t 38 sclk i2s[3:0] lrclk t 37 s c l k l r c l k i n p u t p o r t audio input ports i 2 s signa l assignment i 2 s [ 3 : 0 ] ap_in_sclk ap_in ap_in5 ap_in[4:1] 1 1833-012 aud_in (i2s0 on l y) aud_in_lrclk aud_in_sclk aud_in notes 1. aud_in port not available when ap_in port used. 2. ap_in port not available when pixe l port input used. figure 10 . i 2 s input timing lrclk left right i 2 s s t andard i 2 s form a t = 00 32 clock slots 32 clock slots msb left msb right sclk i2s[3:0] lsb lsb 1 1833-013 figure 11 . i 2 s standard audio , data width 16 to 24 bits per channel left right 16 clock slots 16 clock slots msb left lsb left msb right lsb right lrclk sclk i2s[3:0] lsb 1 1833-014 figure 12 . i 2 s standard audio , 16 - bit sa mples only
data sheet adv7627 rev. 0 | page 11 of 24 lrclk sclk i2s[3:0] msb ? 1 msb ? 1 msb msb msb msb msb msb msb msb lsb lsb left right serial audio right justified i 2 s format = 01 msb extended msb extended 32 clock slots 32 clock slots 1 1833-015 figure 13 . serial audio , right - justified lrclk sclk i2s[3:0] msb msb lsb lsb left right 32 clock slots 32 clock slots serial audio left justified i 2 s format = 10 1 1833-016 figure 14 . serial audio , left - justified lrclk sclk i2s[3:0] channe l a channe l b frame n + 1 frame n p c u v p c u msb v msb lsb lsb 32 clock slots 32 clock slots aes3 direct audio i 2 s form a t = 1 1 1 1833-017 figure 15 . aes3 direct audio t 40 t 41 t 42 ap_in_sclk ap_in[5:0] 1 1833-018 figure 16 . dsd input ti ming
adv7627 data sheet rev. 0 | page 12 of 24 ap_out_sclk l r c l k i2 s x l e f t - j u s t if ie d m o d e i2 s x r ig h t - j u s t if ie d m o d e i2 s x i 2 s m o d e m s b m s b ? 1 t 4 7 t 4 6 t 4 9 t 5 0 t 4 8 m s b m s b ? 1 l s b m s b t 4 9 t 5 0 t 4 9 t 5 0 notes 1. lrclk is a signa l accessible vi a ap_out5. 2. i2sx are signals accessible vi a ap_out1 t o ap_out4. 1 1833-020 figure 17 . i 2 s output timing t 5 1 t 5 3 t 5 2 ap_out_sclk ap_out[5:0] 1 1833-021 figure 18 . dsd output timing power specifications table 3 . parameter symbol min typ max unit power supplies hdmi tx analog power sup ply avdd_tx 1.71 1.8 1.89 v comparator power supply cvdd 1.71 1.8 1.89 v digital power supply dvdd 1.71 1.8 1.89 v digital i/o power supply dvddio 3.14 3.3 3.46 v pll power supply pvdd 1.71 1.8 1.89 v hdmi tx pll power supply pvdd_tx 1.71 1.8 1.89 v termination power supply tvdd 3.14 3.3 3.46 v current consumption mux mode 1 , 2 hdmi tx analog power supply i avdd_tx 2 4 ma comparator power supply i cvdd 96.5 ma digital core power supply i dvdd 173 ma digital i/o power supply i dvddio 1.5 ma pll power supply i pvdd 34 ma hdmi tx pll power supply i pvdd_tx 70 ma termination power supply i tvdd 113 ma
data sheet adv7627 rev. 0 | page 13 of 24 parameter symbol min typ max unit current consumption audio insert mode 1 , 3 hdmi tx analog power supply i avdd_tx 26 ma comparator power supply i cvdd 184 ma digital core power supply i dvdd 216 ma digital i/o power supply i dvddio 0.05 ma pll power supply i pvdd 64.1 ma hdmi tx pll power supply i pvdd_tx 71 ma termination power supply i tvdd 116 ma current co nsumption power - down mode 0 1 , 4 hdmi tx analog power supply i avdd_tx 1.30 ma comparator power supply i cvdd 0.84 ma digital core power supply i dvdd 0.25 ma digital i/o power supply i dvddio 0.21 ma pll power supply i pvdd 0.02 ma hdmi tx pll power supply i pvdd_tx 0. 10 ma termination power supply i tvdd 0.14 ma current consumption power - down mode 1 1 , 5 hdmi tx analog power supply i avdd_tx 1.90 ma comparator power supply i cvdd 0.84 ma digital core power supply i dvdd 0.95 ma digital i/o power supply i dvddio 0.21 ma pll power supply i pvdd 0.02 ma hdmi tx pll power supply i pvdd_tx 0. 10 ma termination power supply i tvdd 0.14 ma current consumption example max imum operating mode 1 , 6 hdmi tx analog power supply i avdd_t x 3 1 .00 ma comparator power supply i cvdd 213.00 ma digital core power supply i dvdd 255 .00 ma digital i/o power supply i dvddio 0.2 0 ma pll power supply i pvdd 7 5 .00 ma hdmi tx pll power supply i pvdd_tx 82 .00 ma termination power supply i tvdd 127.00 ma 1 d ata recorded during lab characteri z ation . typical current consumption values are recorded with nominal voltage supply levels and at room temperature. 2 adv7627 configured in m ux m ode with one active hdmi rx input and the hdmi tx output in use. 4k 2k at 30 hz video format with pseudo random test pattern applied to the active hdmi rx input port. hdmi rx termination closed on the active hdmi rx input port and open on the unuse d hdmi rx input ports. hdmi tx source termination enabled. 3 adv7627 configured in a udio insert m ode with one active hdmi rx input and the hdmi tx output in use . audio inserted on hdmi tx output from the ap_in input port. hbr audio used. no audio extraction. 4k 2k at 30 hz video format with pseudo random test pattern applied to the active hdmi rx input port. hdmi rx port termination closed on the active hdmi rx input port and open on the unused hdmi rx input ports. hdmi tx source termination enabled. osd not enabled. 4 adv7627 configured in power - down mode 0 . in p ower - d own m ode 0, all blocks are powered down except for the i 2 c slave. 5 adv7627 configured in power - down mode 1 . in p ower - d own m ode 1, all blocks are powered down except for the i 2 c slave and the cec (to monitor wake - up interrupts). 6 adv7627 configured in an example maximum operating mode with one active hdmi rx input and the hdmi tx output in use. hbr audio from the active hdmi rx input inserted on t he hdmi tx output . no audio extraction. 4k 2k at 30 hz video format with pseudo random test pattern applied to the act ive hdmi rx input port. hdmi rx port termination closed on the acti ve hdmi rx input port and open on the unused hdmi rx input ports . hdmi tx source termination enabled. osd not enabled. maximum current consumption values recorded with maximum power supply levels at device maximum operating temperature.
adv7627 data sheet rev. 0 | page 14 of 24 absolute maximum rat ings table 4 . parameter rating avdd_tx to gnd 2.2 v cvdd to gnd 2.2 v dvdd to gnd 2.2 v pvdd to gnd 2.2 v pvdd_tx to gnd 2.2 v dvddio to gnd 4.0 v tvdd to gnd 4.0 v digital inputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v up to a maximum of 4.0 v 5 v tolerant digital inputs to gnd 1 5.5 v digital output s voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v up to a maximum of 4.0 v x tal + , x tal ? pins ?0.3 v to pvdd + 0.3 v maximum junction temperature ( t j max ) 125c storage temperature range ?65c to + 150c infrared reflow, soldering (20 sec) 260c 1 the following inputs are 5 v tolerant: ddc_scl_rxa, ddc_sda_rxa, ddc_ scl_rxb, ddc_sda_rxb, ddc_scl_rxc, ddc_sda_rxc, ddc_scl_rxd, ddc_sda_rxd, ddc_scl _rxe, ddc_sda_rxe, rxa_5v, rxb_5v, rxc_5v, rxd_5v, rxe_5v, cec, ddc_scl_tx, ddc_sda_tx, tx_hpd_arc ? , and tx_arc+. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package the rmal performance to reduce power consumption when using the adv7627 , the user is advised to turn off unused sections of the device . due to printed circuit board ( pcb ) metal variation and, theref ore, variation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this solution eliminates the variance a ssociated with the ja value. the maximum junction temperature (t j max ) of 125c must not be exceeded. the following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (dut): t j = t s + ( jt w total ) where: t s is the package surface temperature (c). jt = 0. 41 c/w for the 260- ball csp _ bga (based on 2s2p test board defined in the jedec specification ) . w total = (( pvdd i pvdd ) + ( pvdd_tx i pvdd_tx ) + ( tvdd i tvdd ) + ( cvdd i cvdd ) + ( av d d _ t x i av d d _ t x ) + ( dvdd i dvdd ) + ( dvddio i dvddio )) note that this calculation assumes a configuration of one active hdmi rx input and one active hdmi tx output, where termi - nation is open on the unused rx inp ut ports. esd caution
data sheet adv7627 rev. 0 | page 15 of 24 pin configuration an d function descripti ons a gnd rxa_2+ rxa_1+ rxa_0+ rxa_c+ cvdd rxb_2+ rxb_1+ rxb_0+ rxb_c+ cvdd rxc_2+ rxc_1+ rxc_0+ rxc_c+ cvdd rxc_5v gnd b gnd rxa_2? rxa_1? rxa_0? rxa_c? cvdd rxb_2? rxb_1? rxb_0? rxb_c? cvdd rxc_2? rxc_1? rxc_0? rxc_c? cvdd rxc_h p a gnd c gnd cvdd cvdd tvdd tvdd gnd gnd tvdd tvdd gnd gnd tvdd tvdd gnd gnd cvdd gnd gnd d int1 int2 sc l sd a cs rxa_5v rxa_h p a ddc_ scl_rx a ddc_ sda_rx a ddc_ scl_rxb ddc_ sda_rxb rxb_h p a rxb_5v ddc_ sda_rxc ddc_ scl_rxc tvdd rxd_2? rxd_2+ e nc nc alsb reset rxd_5v tvdd rxd_1? rxd_1+ f nc nc ap_out0 ap_out1 rxd_h p a gnd rxd_0? rxd_0+ g nc nc ap_out2 ap_out3 dvdd dvdd dvdd dvdd dvdd test5 ddc_ scl_rxd gnd rxd_c? rxd_c+ h nc nc ap_out4 ap_out5 dvddio gnd gnd gnd gnd gnd ddc_ sda_rxd gnd cvdd cvdd j ap_out_ mclk ap_out_ sclk test6 test7 dvddio gnd gnd gnd gnd gnd ddc_ scl_rxe tvdd rxe_2? rxe_2+ k gnd gnd test8 aud_in gnd gnd gnd gnd gnd gnd ddc_ sda_rxe tvdd rxe_1? rxe_1+ l xt al+ xt al? aud_in_ sclk aud_in_ lrclk gnd gnd gnd gnd gnd gnd rxe_h p a gnd rxe_0? rxe_0+ m pvdd pvdd test3 test2 gnd gnd gnd gnd gnd gnd rxe_5v gnd rxe_c? rxe_c+ n gnd gnd pvdd_tx pvdd_tx gnd gnd cvdd cvdd p nc nc gnd test14 hs vs test4 test1 r nc nc gnd a vdd_tx tx_hpd_ arc? r_tx gnd tx_arc+ ddc_ sda_tx ddc_ scl_tx cec dvddio ep_cs p9/ap_ in_sclk p1 1/ap_ in4 p13/ap_ in2 p15/ap_ in0 pclk t nc nc gnd a vdd_tx test9 gnd gnd gnd gnd a vdd_tx a vdd_tx dvddio ep_sclk p8/ap_ in_mclk p10/ap_ in5 p12/ap_ in3 p14/ap_ in1 de u nc nc gnd test10 test 1 1 pvdd_tx gnd tx_c+ tx_0+ tx_1+ tx_2+ gnd ep_mosi p1 p3 p5 p7 gnd v gnd gnd gnd test12 test13 pvdd_tx gnd tx_c? tx_0? tx_1? tx_2? gnd ep_miso p0 p2 p4 p6 gnd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 1 1833-023 figure 19 . pin configuration table 5 . pin functio n descriptions pin no. mnemonic function description a1 gnd ground ground . a2 rxa_2+ hdmi rx input hdmi rxa channel 2 true input . a3 rxa_1+ hdmi rx input hdmi rxa channel 1 true input . a4 rxa_0+ hdmi rx input hdmi rxa channel 0 true input . a5 rxa_c+ hdmi rx input hdmi rxa clock true input . a6 cvdd power comparator power supply (1.8 v) . a7 rxb_2+ hdmi rx input hdmi rxb channel 2 true input . a8 rxb_1+ hdmi rx input hdmi rxb channel 1 true input . a9 rxb_0+ hdmi rx input hdmi rxb channel 0 true input . a10 rxb_c+ hdmi rx input hdmi rxb clock true input . a11 cvdd power comparator power supply (1.8 v) . a12 rxc_2+ hdmi rx input hdmi rxc channel 2 true input .
adv7627 data sheet rev. 0 | page 16 of 24 pin no. mnemonic function description a13 rxc_1+ hdmi rx input hdmi rxc channel 1 true input . a14 rxc_0+ hdmi rx input hdmi rxc channel 0 true input . a15 rxc_c+ hdmi rx input hdmi rxc clock true input . a16 cvdd power comparator power supply (1.8 v) . a17 rxc_5v hdmi rx input hdmi rxc 5 v detect pin . a18 gnd ground ground . b1 gnd ground ground . b2 rxa_2 ? hdmi rx input hdmi rxa channel 2 complement input . b3 rxa_1 ? hdmi rx input hdmi rxa channel 1 complement input . b4 rxa_0 ? hdmi rx input hdmi rxa channel 0 complement input . b5 rxa_c ? hdmi rx input hdmi rxa clock complement input . b6 cvdd power compar ator power supply (1.8 v) . b7 rxb_2 ? hdmi rx input hdmi rxb channel 2 complement input . b8 rxb_1 ? hdmi rx input hdmi rxb channel 1 complement input . b9 rxb_0 ? hdmi rx input hdmi rxb channel 0 complement input . b10 rxb_c ? hdmi rx input hdmi rxb clock co mplement input . b11 cvdd power comparator power supply (1.8 v) . b12 rxc_2 ? hdmi rx input hdmi rxc channel 2 complement input . b13 rxc_1 ? hdmi rx input hdmi rxc channel 1 complement input . b14 rxc_0 ? hdmi rx input hdmi rxc channel 0 complement input . b 15 rxc_c ? hdmi rx input hdmi rxc clock complement input . b16 cvdd power comparator power supply (1.8 v) . b17 rxc_hpa hdmi rx out put hdmi rxc hot plug assert . b18 gnd ground ground . c1 gnd ground ground . c2 cvdd power comparator power supply (1.8 v) . c3 cvdd power comparator power supply (1.8 v) . c4 tvdd power hdmi rx terminator supply voltage (3.3 v) . c5 tvdd power hdmi rx terminator supply voltage (3.3 v) . c6 gnd ground ground . c7 gnd ground ground . c8 tvdd power hdmi rx terminator supply voltag e (3.3 v) . c9 tvdd power hdmi rx terminator supply voltage (3.3 v) . c10 gnd ground ground . c11 gnd ground ground . c12 tvdd power hdmi rx terminator supply voltage (3.3 v) . c13 tvdd power hdmi rx terminator supply voltage (3.3 v) . c14 gnd ground groun d . c15 gnd ground ground . c16 cvdd power comparator power supply (1.8 v) . c17 gnd ground ground . c18 gnd ground ground . d1 int1 control interrupt o utput. this pin can be active low or high. when an unmasked status bit changes, an interrupt is generate d on this pin . d2 int2 control interrupt o utput . this pin can be active low or high. when an unmasked status bit changes, an interrupt is generated on this pin . d3 scl i 2 c c ontrol i 2 c clock input. this pin is open drain; connect this pin to a 3.3 v suppl y using a 4.7 k resistor . d4 sda i 2 c c ontrol i 2 c data input. this pin is open drain; connect this pin to a 3.3 v supply using a 4.7 k resistor . d5 cs digital i nput chip select pin. this pin must be set low or left floating for th e chip to process i 2 c messages that are destined for the adv7627 . the adv7627 ignores i 2 c messages when this pin is high. d6 rxa_5v h dmi rx input hdmi rxa 5 v detect pin .
data sheet adv7627 rev. 0 | page 17 of 24 pin no. mnemonic function description d7 rxa_hpa hdmi rx output hdmi rxa hot plug assert . d8 ddc_scl_rxa hdmi rx ddc hdcp slave serial clock for hdmi rxa . d9 ddc_sda_rxa hdmi rx ddc hdcp slave serial data for hdmi rxa . d10 ddc_scl_rxb hdmi rx ddc hdcp slave serial clock for hdmi rxb . d11 ddc_sda_rxb hdmi rx ddc hdcp slave serial data for hdmi rxb . d12 rxb_hpa hdmi rx output hdmi rxb hot plug assert . d13 rxb_5v hdmi rx input hdmi rxb 5 v detect pin . d14 ddc_sda_rxc hdmi rx ddc hdcp slave serial data for hdmi rxc . d15 ddc_scl_rxc hdmi rx ddc hdcp slave serial clock for hdmi rxc . d16 tvdd power hdmi rx terminator supply voltage (3.3 v) . d17 rxd_2 ? hdmi rx input hdmi rxd channel 2 complement input . d18 rxd_2+ hdmi rx input hdmi rxd channel 2 true input . e1 nc do not connect leave this pin floating . e2 nc do not connect leave this pin floating. e3 alsb i 2 c c ontrol pin to set the i 2 c address of t he i/o r egister m ap for the device. when the alsb pin is tied low, the i/o r egister m ap i 2 c address is 0xb0. when the alsb pin is tied high, the i/o r egister m ap i 2 c address is 0xb2. e4 reset miscellaneous d igital reset pin . e15 rx d_5v hdmi rx input hdmi rxd 5 v detect pin . e16 tvdd power hdmi rx terminator supply voltage (3.3 v) . e17 rxd_1 ? hdmi rx input hdmi rxd channel 1 complement input . e18 rxd_1+ hdmi rx input hdmi rxd channel 1 true input . f1 nc do not connect leave this pin floating. f2 nc do not connect leave this pin floating. f3 ap _out0 audio o utput audio output port , output 0 . f4 ap _out1 audio o utput audio output port , output 1 . f15 rxd_hpa hdmi rx output hdmi rxd hot plug assert . f16 gnd ground ground . f17 rxd_0 ? hdmi rx input hdmi rxd channel 0 complement input . f18 rxd_0+ hdmi rx input hdmi rxd channel 0 true input . g 1 nc do not connect leave this pin floating. g2 nc do not connect leave this pin floating. g3 ap _out2 audio o utput audio output port , output 2 . g4 ap _out3 audio o utput audio output port , output 3 . g7 dvdd power digital power supply (1.8 v) . g8 dvdd po wer digital power supply (1.8 v) . g9 dvdd power digital power supply (1.8 v) . g10 dvdd power digital power supply (1.8 v) . g11 dvdd power digital power supply (1.8 v) . g12 test5 test p in test p in 5 . leave this pin floating. g15 ddc_scl_rxd hdmi rx ddc hdcp slave serial clock for hdmi rxd . g16 gnd ground ground . g17 rxd_c ? hdmi rx input hdmi rxd clock complement input . g18 rxd_c+ hdmi rx input hdmi rxd clock true input . h1 nc do not connect leave this pin floating. h2 nc do not connect leave this p in floating. h3 ap _out4 audio o utput audio output port , output 4 . h4 ap _out5 audio o utput audio output port , output 5 . h7 dvddio power digital interface supply (3.3 v) . h8 gnd ground ground . h9 gnd ground ground . h10 gnd ground ground . h11 gnd groun d ground .
adv7627 data sheet rev. 0 | page 18 of 24 pin no. mnemonic function description h12 gnd ground ground . h15 ddc_sda_rxd hdmi rx ddc hdcp slave serial data for hdmi rxd . h16 gnd ground ground . h17 cvdd power comparator power supply (1.8 v) . h18 cvdd power comparator power supply (1.8 v) . j1 ap _out_mclk audio o utput audio output port , mclk . j2 ap _out_sclk audio o utput audio output port , sclk . j3 test6 test pin connect this pin to ground using a 4.7 k resistor. j4 test7 test pin connect this pin to ground using a 4.7 k resistor. j7 dvddio power digital interface suppl y (3.3 v) . j8 gnd ground ground . j9 gnd ground ground . j10 gnd ground ground . j11 gnd ground ground . j12 gnd ground ground . j15 ddc_scl_rxe hdmi rx ddc hdcp slave serial clock for hdmi rxe . j16 tvdd power hdmi rx terminator supply voltage (3.3 v) . j17 rxe_2 ? hdmi rx input hdmi rxe channel 2 complement input . j18 rxe_2+ hdmi rx input hdmi rxe channel 2 true input . k1 gnd ground ground . k2 gnd ground ground . k3 test8 test pin connect this pin to ground using a 4.7 k resistor. k4 aud _in audio i nput audio input port , i 2 s or s/ pdif input . k7 gnd ground ground. k8 gnd ground ground. k9 gnd ground ground. k10 gnd ground ground. k11 gnd ground ground. k12 gnd ground ground. k15 ddc_sda_rxe hdmi rx ddc hdcp slave serial data for hdmi rxe . k16 tvdd power hdmi rx terminator supply voltage (3.3 v) . k17 rxe_1 ? hdmi rx input hdmi rxe channel 1 complement input . k18 rxe_1+ hdmi rx input hdmi rxe channel 1 true input . l1 x tal+ miscellaneous d igital adv7627 crystal input . l2 x tal ? miscellaneous d igita l adv7627 crystal output . l3 aud_in_sclk audio i nput audio input port , sclk . l4 aud_in_lrclk audio i nput audio input port , lrclk . l7 gnd ground ground . l8 gnd ground ground . l9 gnd ground gr ound . l10 gnd ground ground . l11 gnd ground ground . l12 gnd ground ground . l15 rxe_hpa hdmi rx output hdmi rxe hot plug assert . l16 gnd ground ground . l17 rxe_0 ? hdmi rx input hdmi rxe channel 0 complement input . l18 rxe_0+ hdmi rx input hdmi rxe channel 0 true input . m1 pvdd power pll digital supply (1.8 v) . m2 pvdd power pll digital supply (1.8 v) . m3 test3 test p in test p in 3 . leave this pin floating. m4 test2 test p in test p in 2 . leave this pin floating. m7 gnd ground ground . m8 gnd ground ground .
data sheet adv7627 rev. 0 | page 19 of 24 pin no. mnemonic function description m9 gnd ground ground . m10 gnd ground ground . m11 gnd ground ground . m12 gnd ground ground . m15 rxe_5v hdmi rx input hdmi rxe 5 v detect pin . m16 gnd gro und ground . m17 rxe_c ? hdmi rx input hdmi rxe clock complement input . m18 rxe_c+ hdmi rx input hdmi rxe clock true input . n1 gnd ground ground . n2 gnd ground ground . n3 pvdd_tx power hdmi tx pll power supply (1.8 v) . n4 pvdd_tx power hdmi tx pll power supply (1.8 v) . n15 gnd ground ground . n16 gnd ground ground . n17 cvdd power comparator power supply (1.8 v) . n18 cvdd power comparator power supply (1.8 v) . p1 nc do not connect leave this pin floating. p2 nc do not connect leave this pin floating. p3 gnd ground groun d . p4 test14 test pin connect this pin to ground using a 4.7 k resistor. p15 hs pixel port input s ync horizontal sync hronization for pixel port input video . p16 vs pixel port input s ync vertical sync hronization for pixel port input video . p17 test4 test p in test p in 4 . leave this pin floating. p18 test1 test p in test p in 1 . leave this pin floating. r1 nc do not connect leave this pin floating. r2 nc do not connect leave this pin floating. r3 gnd ground ground . r4 avdd_tx power hdmi tx analog supply (1.8 v) . r5 tx_hpd_arc ? hdmi tx in put hdmi tx hot plug detec t (hpd) signal and audio return channel complement input. r6 r_tx hdmi tx in put this pin s ets the i nternal r eference c urrents for hdmi tx. place a 470 resistor (1% tolerance) between this pin and gnd . place t he external resistor as close as possible to the adv7627 . r7 gnd ground ground . r8 tx_arc+ hdmi tx in put hdmi tx audio return channel true input . r9 ddc_sda_tx hdmi tx ddc hdcp slave serial data for hdmi tx . r10 ddc_scl_tx hdmi tx ddc h dcp slave serial clock for hdmi tx . r11 cec hdmi tx cec hdmi tx consumer electronics control (cec) . r12 dvddio power digital interface supply (3.3 v) . r13 ep_ cs serial p ort c ontrol spi chip select interface for the osd . r14 p9/ ap _in_sclk pixel p ort i nput/ a udio i nput pixe l port input p9/audio input port , sclk . r15 p11/ ap _in4 pixel p ort i nput/ a udio i nput pixel port input p11/audio input port , input 4 . r16 p13/ ap _in2 pixel p ort i nput/ a udio i nput pixel port input p13/audio input por t , input 2 . r17 p15/ ap _in0 pixel p ort i nput/ a udio i nput pixel port input p15/audio input port , input 0 . r18 pclk pixel port input clock pixel clock for pixel port input video . t1 nc do not connect leave this pin floating. t2 nc do not connect leave thi s pin floating. t3 gnd ground ground . t4 avdd_tx power hdmi tx analog supply (1.8 v) . t5 test9 test pin connect this pin to ground using a 4.7 k resistor. t6 gnd ground ground . t7 gnd ground ground . t8 gnd ground ground . t9 gnd ground ground .
adv7627 data sheet rev. 0 | page 20 of 24 pin no. mnemonic function description t10 avdd_tx power hdmi tx analog supply (1.8 v) . t11 avdd_tx power hdmi tx analog supply (1.8 v) . t12 dvddio power digital interface supply (3.3 v) . t13 ep_sclk serial p ort c ontrol spi clock interface for the osd . t14 p8/ ap _in_mclk pixel p ort i nput/ a udio i nput pixel port input p8/audio input port , mclk . t15 p10/ ap _in5 pixel p ort i nput/ a udio i nput pixel port input p10/audio input port , input 5 . t16 p12/ ap _in3 pixel p ort i nput/ a udio i nput pixel port input p12/audio input port , input 3 . t17 p14/ ap _in1 pixel p ort i nput/ a udio i nput pixel port input p14/audio input port , input 1 . t18 de pixel port input s ync data enable for pixel port input video . u1 nc do not connect leave this pin floating. u2 nc do not connect leave this pin floating. u3 gnd ground groun d . u4 test10 test pin connect this pin to ground using a 4.7 k resistor. u5 test11 test pin connect this pin to ground using a 4.7 k resistor. u6 pvdd_tx power hdmi tx pll power supply (1.8 v) . u7 gnd ground ground . u8 tx_c+ hdmi tx o utput hdmi tx clock true output . u9 tx_0+ hdmi tx o utput hdmi tx channel 0 tr ue output . u10 tx_1+ hdmi tx o utput hdmi tx channel 1 true output . u11 tx_2+ hdmi tx o utput hdmi tx channel 2 true output . u12 gnd ground ground . u13 ep_mosi serial p ort c ontrol spi master out put /slave in put for osd . u14 p1 pixel p ort i nput pixel port input p1 . u15 p3 pixel p ort i nput pixel port input p3 . u16 p5 pixel p ort i nput pixel port input p5 . u17 p7 pixel p ort i nput pixel port input p7 . u18 gnd ground ground . v1 gnd ground ground . v2 gnd ground ground . v3 gnd ground ground . v4 test12 tes t pin connect this pin to ground using a 4.7 k resistor. v5 test13 test pin connect this pin to ground using a 4.7 k resistor. v6 pvdd_tx power hdmi tx pll power supply (1.8 v) . v7 gnd ground ground . v8 tx_c ? hdmi tx o utput hdmi tx clock complement o utput . v9 tx_0 ? hdmi tx o utput hdmi tx channel 0 complement output . v10 tx_1 ? hdmi tx o utput hdmi tx channel 1 complement output . v11 tx_2 ? hdmi tx o utput hdmi tx channel 2 complement output . v12 gnd ground ground . v13 ep_miso serial p ort c ontrol spi master in put /slave out put for osd . v14 p0 pixel p ort i nput pixel port input p0 . v15 p2 pixel p ort i nput pixel port input p2 . v16 p4 pixel p ort i nput pixel port input p4 . v17 p6 pixel p ort i nput pixel port input p6 . v18 gnd ground ground .
data sheet adv7627 rev. 0 | page 21 of 24 p ower supply recommendation s power - up sequence the power - up sequence for the adv7627 is as follows : 1. hold the reset pin low. 2. power up the 3.3 v supplies (dvddio and tvdd). 3. after the 3.3 v supplies reach their minimum recommended value of 3.14 v , wait at least 20 ms before powering up the 1.8 v supplies. 4. power up the 1.8 v supplies (avdd_tx, cvdd, dvdd, pvdd, and pvdd_tx). these supplies s hould be powered up at the same time; that is, there should be a difference of less than 0.3 v between them. 5. release the reset pin after all supplies are established . a fter power - up , a complete reset is recommended . this reset can be performed by the system microcontroller. t pss 20ms r e s e t > 5 m s reset 1 . 8 v s u p p l y 3 . 3 v s u p p l y 0 v 0 v 0 v 3 . 3 v 3 . 3 v 1 . 8 v 3 . 1 4 v 1 1833-022 figure 20 . adv7627 supply power - up sequence power - down sequence the adv7627 supplies can be de asserted simultaneously as l ong as dvddio or tvdd does not fall below a lower rated supply.
adv7627 data sheet rev. 0 | page 22 of 24 theory of operation hdmi receiver the adv7627 front end incorporates a 5:1 multiplexed hdmi receiver capable of receiving all h dtv formats up to 3 ghz (4k 2k at 24 hz /25 hz /30 hz) . the hdmi receiver also sup - port s hdmi features including 3d tv and content type bits . the hdmi receiver in the adv7627 incorporates an ada ptive equalizer , which compensates for the high frequency losses inherent in hdmi and dvi cabling, especially at longer lengths and higher frequencies. the adv7627 features a 768 - byte internal ed id memory space , which can be used to store two independent edids . the memory can be partitioned to provide two 256 - byte edids or one 512 - byte extended edid and one 256 - byte edid. either edid can be replicat ed on any input port . the hdmi receiver offer s ad vanced audio functionality. the receiver support s multichannel i 2 s audio for up to eight channels. the receiver also suppor ts a six - dsd channel interface , wit h each channel carrying an over sampled 1 - bit representation of the audio signal as delivered on sa cd. the adv7627 can also receive hbr audio packet streams and output them through the hbr interface in an s/pdif format that conform s to the iec 60958 standard. s/pdif is supported via the hpd ba ck channel. the receiver also contain s an audio mute controller that can detect a variety of conditions that can result in audible extraneous noise in the audio output. on detection of these conditions, the audio data can be ramped to prevent audio clicks or pops. hdcp repeater functionali ty with the inclusion of hdcp 1.4, displays can receive encrypted video content. the hdmi interface of the adv7627 allows authentication of a video receiver, dec ryption of encoded data at the receiver, and renewability of that authentication during trans - mission , as specified by the hdcp 1.4 protocol. repeater support is also offered by the adv7627 . digi tal audio ports the adv7627 features an audio input port and an audio output port . the audio input and output ports provide comprehensive muxing support for the destination of the audio ( for exam ple, to the hdmi transmitter or audio output port) and support for the source of the audio ( for example, from the hdmi receiver or from the audio input port). the extracted audi o can be processed by a sharc? p rocessor and can be reinserted back into the hdmi output stream or output via the hardware connected to the system. the pins for the p ixel p ort i nput signals ( p15 to p 8 ) are shared with the ap_in audio input port. when the p ixel p ort i nput is in use, the a ud _in port can be used to provide stereo audio input. on - screen display a key feature of the adv7627 is the on - chip character - and icon - based osd generator. the generated osd can be converted to match the 4:2:2 or 4:4:4 input format in either the rgb or ycrcb color spaces. after the osd is generated, it is overlaid at the output resolution (any video resolution up to 4k 2k at 24 hz/25 hz/30 hz ) for best performance. the osd portion of the imag e is optionally semitransparent using a 5 - bit alpha blend betwe en the input video and the osd. the osd font characters and icons can be stored in external spi flash memory, read directly into ram, or they can be loaded in to the on - chip ram via the spi or i 2 c interface . pixel port input the adv7627 features a 16 - bit pixel input port that facilitates the reception of digital video data from a n analog front - end video decoder such as the adv7180 , adv7181d , or adv7842 . both embedded timing and external sync hronization sign als are supported on the pixel port. the pixel port input also features an interlaced - to - progressive converter for 480i or 576i inputs . hdmi transmitter the adv7627 incorporates an hdmi transmitt er , which support s all hdtv formats up to 3 ghz ( 4k 2k at 24 hz/25 hz/30 hz ), arc , and all mandatory 3d tv formats. the hdmi transmitter can output any audio mode received from the hdmi receiver , including au dio sample packets, hbr , or dsd. the arc recei ver s upport s both single - ended and differential modes and simplifies cabling by combining an upstream audio capability in a conventional hdmi cable. the transmitter features an on - chip mpu with an i 2 c master to perform hdcp opera - tions and edid read operat ions. i 2 c interface the adv7627 supports a 2 - wire serial (i 2 c - compatible) micro processor bus driving multiple peripherals. the adv7627 is controlled by an external i 2 c master devi ce, such as a micro - controller. other features other features of t he adv7627 include the following: ? fully qualified software low level libraries, driv er, and application ? complete input and output audio support ? programmable interrupt request output pins: int1 and int2 ? chip select and alsb ? low power consumption: 1.8 v digital core, 1.8 v analog, and 3.3 v digital input/output ? temperature range: 0c to 70 c ? 15 mm 15 mm, pb - free, 260- ball csp_ bga
data sheet adv7627 rev. 0 | page 23 of 24 outline dimensions a b c d e f g 9 8 11 10 13 12 7 6 5 4 2 3 1 13.60 bsc sq h j k l m n p r t u v 0.35 nom 0.30 min 15.10 15.00 sq 14.90 1.50 1.36 1.21 1.11 1.01 0.91 15 14 17 16 18 compliant to jedec standards mo-275-kkab-1. 1 1-18-2013-b 0.50 0.45 0.40 coplanarit y 0.20 ball diameter 0.80 bsc de t ai l a a1 ball corner a1 ball corner detail a bottom view top view seating plane figure 21 . 260 - ball chip scale package ball grid array [csp_bga] (bc - 260 - 1) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package des cription package option adv762 7 kbcz -8 0c to 70c 260- ball chip scale package ball grid array [csp _ bga] bc -260-1 adv762 7 kbcz -8 -rl 0c to 70c 260- ball chip scale package ball grid array [csp _ bga] bc -260-1 eval - adv7625 -sm z evaluation board 1 z = rohs compliant part. 2 this part is programmed with internal hdcp keys. customers must have hdcp adopter status (consult digital content protection, llc, for licensing requirements) to purchase any components with internal hdcp keys.
adv7627 data sheet rev. 0 | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors) . hdmi, the hdmi logo, and high - definition multimedia interface are trademarks or registered trademarks of hdmi li censing llc in the united states and other countries. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11833 - 0 - 12/13(0)

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